The present invention relates to integrated circuit (IC) packaging technology, and more particularly, to an IC package having improved protection from electro-static discharges.
Integrated circuits (IC) having thousands or even millions of electronic components and circuit elements are fabricated on an IC die over a semiconductor substrate such as silicon. In this document, the phrase “IC die” includes the electronic components and circuit elements within the IC die. To electrically connect the IC die to other electronic components and to protect the IC die, the IC die is typically packaged within an IC package. A sample IC package 10 is illustrated in FIG. 1A in a perspective view. The IC package 10 often has plastic or ceramic body 14 and encases the IC die within the IC package 10. Further, the IC package 10 includes connection means 11 and 12 to connect, electrically and mechanically, the IC package 10 to other electronic components. For convenience, the connection means 11 and 12 are illustrated as pins 11 and 12; however, it is understood in the art that the connection means 11 and 12 can include other implementations such as ball grid array, connection pad, or others depending in the desired application. To avoid clutter, only two of the twelve illustrated pins are designated with the reference numerals 11 and 12; however, it is known in the industry that the IC package 10 can include any number of pins or connections means including, for example, hundreds of pins.
FIG. 1B illustrates a cut-away top view of the IC package 10 showing the IC die, designated with reference numeral 20, encased within the IC package 10. The IC die 20 is connected to the pins 11 and 12 via lead traces 31 and 32 fabricated over a bottom portion 16 of the IC package 10. Again, to avoid clutter, only two of the twelve illustrated lead traces are designated with the reference numerals 31 and 32; however, it is known in the industry that the IC package 10 can include any number of lead traces. In general, reference number 30 is used to refer to all the lead traces of the IC package 10.
The bottom portion 16 is often called a package substrate 16. Each of the lead traces 31 and 32 are electrically and mechanically connected to an input-output (IO) port (via connection pads on the IC die 20) of the IC die 20 via wire bonds 22 or other suitable methods. To avoid clutter, the electronic and circuit elements within the IC die 20 are not illustrated in the Figures. Also to avoid clutter, only two of the multiple wire bonds are desiganted with reference number 22; however, it is know in the industry that any or all traces can be connected to the IC die 20 via wire bonds 22.
The IC die 20 typically operates at 1.5 to 5 volts (v) depending on implementation. That is, each of the lead traces 30 of the IC package 10 typically carries electrical signals at 1.5 to 5 volts. However, the IC die 20 is often designed and manufactured to withstand temporary voltage spikes of up to two (2) kilovolts (kV) introduced to each of its IO ports. This is because surrounding components or environmental factors may introduce electrostatic discharges (ESD) to pins 11 and 12 (of the IC package 10) which are connected to the IO ports of the IC die 20 via the lead traces 30. Electrostatic discharge (ESD) is the release of static electricity when two objects come into contact. In fact, the IC package 10 may be exposed to even higher level of ESD voltage spikes from which the IC die 20 should protected. To protect the IC die 20 from failure, it would be desirable to reduce or minimize the severity of the ESD spike reaching the IO ports of the IC die 20.